FPGAs are a type of Programmable Logic Device. They are generally based on a standard programmable Logic Block, a large number of which are arranged together to implement various functions.
FIG. 1 shows schematically an example of an FPGA system as known in the state of the art.
As shown in FIG. 1, an FPGA chip 10 comprises a number of Logic Blocks 11, for example as described above. The chip also comprises a number of input/output ports 12. Connecting these logic blocks 11 and input/output ports 12 are a number of tracks 14. At junction points of these tracks are provided and number of programmable routing areas 13. In these programmable routing areas there are provided switches which can selectively connect any pair of intersecting tracks, under the control of a logical value stored in a memory cell connected with each switch. The switch memory values are set at system start up from a non volatile memory. Accordingly, by setting the values in the switch memories as required, any connections of any Logic Block can be coupled to those of any other Logic Block, or any input/output port 12. Thus, by properly configuring the memory units to define the operation of each logic block, and the switch memories 13 to establish appropriate connections between the logic blocks, any desired functionality can be implemented.
FIG. 2 shows further detail of elements of an FPGA system as known in the state of the art.
The elements shown in FIG. 2 constitute a representative example of a partial implementation of parts of the functionality described above with respect to FIG. 1.
As shown in FIG. 2, there is provided a first Look Up Table (LUT) 21, and a second Look Up Table (LUT) 22, and a number of further LUTs (not shown). The first LUT 21 comprises seven two input multiplexers 211, 212, 213, 214, 215, 216, 217 respectively. The second LUT and further LUTs are configured similarly. These multiplexers are arranged in a cascading manner with three rows so as to constitute an 8 input multiplexer, the output of which constitutes the output of the LUT. The first row of multiplexers (211, 213, 215 and 217) in each cascade arrangement both have a total of eight inputs. These eight inputs constitute the programming inputs of the first LUT 21. The selection inputs of each row are ganged together, to constitute the three data inputs of the LUT. The data inputs and data output of the first LUT are connected to a set of tracks 2501, 2502. The inputs and outputs of the second and further LUTs are connected correspondingly to a network of further tracks (not shown). Conventionally a LUT with 3 data inputs in this manner is referred to as a “LUT3”. Each of the eight programming inputs of the first LUT 21 connected to a respective Static RAM memory device 251, 252, 253, 254, 255, 256, 257, 258. Corresponding Static RAM memory devices provide the configuration inputs of the second LUT 22, and the other LUTs provided in the system (not shown). In operation, these memory devices 251, 252, 253, 254, 255, 256, 257, 258 provides a constant predetermined logical value to each of the eight programming inputs of each LUT. The content of each SRAM cell is shown schematically as comprising a latch built of two inverters, each receiving the output of the other, with a transistor switch, switched by a word line 23, provided to enable the selective output of the value on the output of one of the inverters in the latch to a bit line connected to a respective configuration input of the LUT 217, and also to a data line 24 by means of which the value of the latch may be set. The bit line of each memory device 251, 252, 253, 254, 255, 256, 257, 258 is connected to a selection bus 24, and the word line of each memory device 251, 252, 253, 254, 255, 256, 257, 258 is connected to a data bus 23. During an initiation phase for the circuit, each memory device 251, 252, 253, 254, 255, 256, 257, 258 is addressed in turn, and the desired value set to the latch in question. The logical behavior of the LUT is response to any binary value on its three data inputs can thus be defined as required. This is the underlying basic concept of FPGA technology. It will be appreciated however that the functions that a single Logic block comprising two LUT3s can implement is limited, however by interconnecting a number of suitably configured LUTs as described above, any arbitrary combinatorial function can be implemented. This interconnection is achieved through a programmable interconnection of the data channels 2501, 2502, and further channels (not shown) carrying data from other LUTs. As shown whilst channels 2501, 2502 are arranged vertically, there is provided a further channel 2503 intersecting channels 2501, 2502. At the intersection of respective lines of channels 2501 and 2503 is provided a programmable switching unit 26. Considering that the intersection of the two lines constitutes a total of four connections at the switching unit, the switching unit comprises 6 transistor switches, arranged to make or break a connection between any two of these four connections. Each of these transistor switches is set to be open or closed by a value received from a respective static memory unit 261, 262, 263, 264, 265, 266. Further such programmable switching units, with corresponding static memory devices are provided at many or all intersection of tracks (not shown). These static memory devices 261, 262, 263, 264, 265, 266 as shown are identical to the memory devices 251, 252, 253, 254, 255, 256, 257, 258, and connected to the same address and data busses 23 and 24, so that when during an initiation phase for the circuit, both the LUT memory devices and switch memory devices may be addressed in turn, and the desired value set to the latch in question, so that the behavior of each LUT, and its connections to any other LUT may be configured as required.
WO2012/123243 A1, U.S. Pat. Nos. 7,463,056 B1, 6,021,513 A, 5,432,441 A, 8,091,001 B2, 5,675,589 A, and 5,027,355 A describe certain aspects of the foregoing.
The article entitled “Bridging the Gap between Soft and Hard eFPGA Design”, by Victor Olubunmi Aken'Ova chapter 3.22 available from https://www.ece.ubc.ca/-lemieux/publications/akenova-masc2005.pdf provides further background information.
While the approach described is highly flexible, it will be appreciated that the interconnection tracks between LUTs and the Address and data busses of the memory units take a significant amount of space. Even in the highly simplified arrangement of FIG. 2 the number of lines shown is substantial, and this quickly becomes onerous in any real implementation. This is further exacerbated by the need to implement testing functionality in the circuit, provided to confirm proper behavior when the device is manufactured, which will require the addition of still further features.